EE 552 Asynchronous VLSI Design
This course introduces students to the emerging field of asynchronous VLSI design.
Asynchronous design has been an active area of research for the past 20 years. Many promising asynchronous design styles and computer-aided-design tools and flows have been developed. Moreover, deep-submicron designs are making the conventional synchronous design alternatives more and more costly and inefficient.
Several companies are taking advantage of this technology for high-performance, low-power, reduce electro-magnetic interference and others are actively exploring this technology. In particular, these circuits are essential in the emerging design trend of globally asynchronous locally synchronous design (GALS). Topics will include traditional hazard-free logic design and state assignment in fundamental mode asynchronous finite state machines, along with modern quasi-delay-insensitive, speed-independent, timed, and template-based design styles. In addition, newer CAD topics of performance analysis and pipeline optimization will be covered.
This course will study the various design styles and provide students with hands-on experience with some of the current state-of-the-art asynchronous tools, including SystemVerilogCSP to model asynchronous architectures and the Proteus tool flow for implementation. A class project will enable students to study asynchronous architectures and design with one of several promising design styles.
This course is taught each Spring at USC and typically has an enrollment of close to 40 students.
Topics include asynchronous channels and architectures; implementation design styles; controller synthesis; hazards and races; Petri-nets; performance analysis and optimization; synchronizers and globally asynchronous locally synchronous design.