Blade - Bundled Data Resilient Design

The periodic nature of the global clock in traditional synchronous designs forces circuits to be margined for the worst possible case of process, voltage, temperature, and data conditions, pariticularly at low and near-threshold voltage supplies. This constrains the silicon to operate at worst-case frequencies and at conservative voltages. Resilient architectures promise to remove these margins, by detecting and correcting timing errors when they occur, thereby creating the potential to achieve real average-case operation. However, synchronous resilient schemes previously proposed either suffer from lack of robustness to metastability or require often complex changes to the architecture, to support replay-based recovery from timing errors. These problems respectively lead to circuit failures or incur high timing penalties when errors occur.

The main target of this research is the development of a new asynchronous bundled-data resilient template called Blade that is robust to metastability issues, requires no replay-based logic, and has low timing error penalties.The pipeline stages in Blade use single-rail logic followed by Transition Detecting Time Borrowing (TDTB) based error-detecting logic and two reconfigurable delay lines.
The stage-to-stage delay line is of duration δ and controls when the TDTB goes transparent and begins to propagate data at the output of the combinational logic to the next stage. The second delay line is of duration Δ and defines a time window during which late transitions that violate this assumption (i.e., timing errors) are allowed, which is called the the timing resiliency window (TRW).

The research focuses on efficient circuit design, computer-aided design, verification, and test. Several relevant pubiished papers include:

  1. D. Hand, M. Moreira, H.-H. Huang, D. Chen, F. Butzke, Z. Li, M. Gibiluka, M. A. Breuer, N. L. V. Calazans, P. A. Beerel: Blade - A Timing Violation Resilient Asynchronous Template. ASYNC 2015: 21-28
  2. D. Hand, H.-H. Huang, B. Cheng, Y. Zhang, M. Moreira, M. A. Breuer, N. L. V. Calazans, P. A. Beerel: Performance Optimization and Analysis of Blade Designs under Delay Variability. ASYNC 2015: 61-68
  3. Y. Zhang, L. S. Heck, . M. Moreira, D. Zar, M. A. Breuer, N. L. V. Calazans, P. A. Beerel: Design and Analysis of Testable Mutual Exclusion Elements. ASYNC 2015: 124-131
  4. M. Moreira, D. Hand, P. A. Beerel, N. Calazans: TDTB error detecting latches: Timing violation sensitivity analysis and optimization. ISQED 2015: 379-383
  5. G. Heck, L. S. Heck, A. Singhvi, M. Moreira, P. A. Beerel, N. L. V. Calazans: Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits. VLSI Design 2015: 321-326.
  6. A. Singhvi, M. T. Moreira, R. N. Tadros, N. L. V. Calazans, P. A. Beerel: A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies, ISLVSI 2015
  7. P. A. Beerel, N. Calazans: A Path Towards Average Case Silicon using Resilient Bundled Data Design, ECCTD 2015 (Invited)
  8. P. A. Beerel: A Path Towards Average Case Silicon via Bundled-Data Resilient Design, Keynote Lecture, Chip-In, Bahia, Brazil, September 8th, 2015.(Slides are available here.)