LAST

LAST is an integrated computer-aided design tool for large-scale channel-based asynchronous architectures, providing a unifying high-level synthesis framework for multiple micro-architectural and circuit design styles. LAST integrates the analysis and optimization modules which explore a wide design spaces and chooses the best design based on given constraints and/or objective functions.  LAST also includes a simulation module to model and simulate the design in Verilogusing Send/Receive handshaking.


Group Members

  1. Prof. Peter A. Beerel (This email address is being protected from spambots. You need JavaScript enabled to view it.)

  2. Sunan Tugsinavisut (This email address is being protected from spambots. You need JavaScript enabled to view it.)

  3.  Nam Hoon Kim (This email address is being protected from spambots. You need JavaScript enabled to view it." style="">This email address is being protected from spambots. You need JavaScript enabled to view it.)

  4. Arash Saifhashemi (This email address is being protected from spambots. You need JavaScript enabled to view it.)

  5. Roger Su (This email address is being protected from spambots. You need JavaScript enabled to view it.)

  6. Prof. Steven M. Nowick (This email address is being protected from spambots. You need JavaScript enabled to view it.)

  7.  Peggy B. McGee (This email address is being protected from spambots. You need JavaScript enabled to view it.)

Please contact me at This email address is being protected from spambots. You need JavaScript enabled to view it. if you have any suggestions or questions.

Goals

  • To synthesize and optimize channel-based asynchronous architectures from a high-level specification.

  • To offer a variety of design spaces by exploring, analyzing and optimizing the design with respect to given constraints and/or objective functions.

  • To construct a synthesis framework for which new optimizations can be easily integrated.

Approaches

  • A system architecture is modeled by a high-level specification (Marked graphs).

  • Analysis and optimizations are performed iteratively to explore and analyze the design choices.

  • The potential set of optimization to explore include

    • Functional resource sharing

    • Register sharing

    • Channel sharing/multiplexing/symmetrization ala Michael

    • Loop unrolling

  • After synthesis, the design is translated into VerilogCSP, where it can be simulated and tested

Current Projects

  • Scheduling and binding problem using heuristic approaches.
    • List Scheduling - Iterating over time steps, dynamically compute the slack of each unscheduled operation, greedily scheduling the operations with the least slack.

Downloads

Publications

  • Sunan Tugsinavisut, Roger Su, Peter A. Beerel: High-level Synthesis for Highly Concurrent Hardware Systems. ACSD 2006: 79-90

Acknowledgements

  • LAST is part of the CaSCADE tool package, a joint project between USC and Columbia University. The CaSCADE tool package release was made possible by generous support from NSF ITR Award No. NSF-CCR-0086036. 
  • The development of the individual tools in CaSCADE was supported in part by the above NSF grant, and by some additional funding (see each downloaded tool individually for further information).