The tool, developed by Wei-Chun Chou as part of his PhD thesis, is written within the USC POSE system which itself is written on top of the Berkeley's SIS environment. Wei-Chun is a recent PhD graduate of the USC Async Group and his related publications can also be found on the USC ASYNC group's publication page
To use AVEmap, you have two choices. You can download the core executables or download the source for the core code and re-compile. For mapping burst-mode circuits, you may also want to download a side-program, PatGen, which can automatically generate the necessary input files for the core program
Dowloading Executables for the Core Program
Download SIS-POSE-AVEmap executable for Solaris.
Download SIS-POSE-AVEmap executable for Linux.
Or, if you want to compile your own executable, please download SIS source code, patch files, and readme files here or at Berkeley's Design Technology Warehouse website. Uncompress sis-1.2.tar.Z, sis-1.2.patch1.Z and sis-1.2.patch-Solaris.Z. Extract (tar xvf) sis-1.2.tar. Follow README-sis and README-Solaris to patch sis-1.2.patch1 and sis-1.2.patch-Solaris. Make necessary changes in Makefiles (Please see README-wcc).
If you want to install SIS in Linux, you only need patch sis-1.2.patch1 (check README-sis). POSE and AVEmap can be compiled and are runnable in both Solaris and Linux. Check README-wcc for Linux.
Download POSE source code here or at USC Advanced Design Automation Lab website of Professor Pedram's group. Put pose-1.1.tar.Z in directory ~sis-1.2/sis. Uncompress and extract it. This will give you a README.install and source code (pose.tar) for POSE. Follow README.install to continue POSE installation. There are some errors in POSE source code and Makefiles. Please check README-wcc for corrections.
Download AVEmap source code. Put avemap.tar.Z in directory ~pose/power_map. Uncompress and extract it. Modify Makefile in power_map to include AVEmap .c files. Compile SIS in ~sis to get an executable which links SIS, POSE, and AVEmap in ~sis. You can also further compile POSE in ~pose to get an executable in ~pose. Please check README-wcc for details.
Beware that the AVEmap source code is not well-documented yet. If you have hard time to understand those C code I wrote, please wait. I am working on documenting the source code now.
Input Description Format
AVEmap inputs are BLIF files and pattern files. For example, if you want to map the scsi bust-mode controller, you need an unmapped scsi.blif and a pattern file scsi.pattern. BLIF is Berkeley's netlist format, described in the SIS_paper.ps included in sis-1.2.tar. A pattern file contains all interested input patterns and their corresponding probabilities. The syntax of this file is described in README-wcc.
PatGen: A Pattern Generation Program for Burst-Mode Circuits
For burst-mode circuits, both BLIF files and pattern files can be automatically generated by PatGen from corresponding verilog files (.v) and 3D spec files (.unc). For example, PatGen reads scsi.v and scsi.unc to generate scsi.blif and scsi.pattern. For one-hot domino circuits, you must manually specify BLIF and pattern files.
Notice that AVEmap only maps combinational part of burst-mode circuits. PatGen automatically removes the feedback networks from input verilog files to generate the output BLIF files without feedback networks. However, when running, AVEmap needs to understand the link between outputs/state variables and corresponding fedback inputs. So, AVEmap reads in .fb.info files which store the fedback inputs of each output and state variable. README-wcc describes how to run PatGen, the format of pattern files, and how to run AVEmap in detail.
Download PatGen source code (patgen.tar.Z), verilog files and unc files (ver+unc.tar.Z), scripts for running AVEmap (lib2.tar), and feedback information of verilog files (fbinfo.tar).
Beware that PatGen was initially created for a power estimation tool and thus has many routines and structures that are not relevant. I am still working on cleaning up the irrelevant parts.