High-Speed Asynchronous Pipeline Cell
Library
(PCHB and STFB), release v1.0
Release v1.0,
November 21, 2007
Cell libraries are the
building blocks for design and are the foundation of
a fully-automated back-end place-and-route design
flow. Many asynchronous design styles use
non-standard components that cannot be found in
commercially-available cell libraries. Current
asynchronous designers rely on full-custom design,
which is time consuming or non-optimal technology
mappings onto available cells.
Demonstrating that new
asynchronous standard-cell libraries can be
developed along with associated place-and-route
flows for asynchronous designs is thus a critical
step in their wide-spread adoption. This is
particularly true for high-performance domino-based
asynchronous design styles which rely on a
wide-range of domino logic building blocks that are
well-known to yield very high-performance but are
not available in commercial cell libraries.
The USC-lead team has
developed two domino-based back-end cell libraries
in TSMC 0.25 technology. The first implements the
pre-charged half-buffer (PCHB) template. And the
second implements the STFB template. Each library
consists of documentation, layout (GDS), and LEF
format, suitable for commercially-standard back-end
place and route tools. Both detailed documentation
and the tarred GDS libraries accessible through the
MOSIS Education Program Cooperative IP Program
which enables downloading of the GDS and
documentation via their
secure document access web page. Note that you
must have an account with MOSIS and have been
granted access to the TSMC 0.25 documents. See the
MOSIS web site
www.mosis.org for more details.
Related Articles:
An Asynchronous
Low-Power High-Performance Sequential Decoder
Implemented With QDI Templates. R. O. Ozdag,
P. A. Beerel, IEEE Transactions on Very Large
Scale Integration (VLSI) Systems, vol.14, no.9,
pp.975-985, Sept. 2006
Back-Annotation in
High-Speed Asynchronous Design. P. Golani
and P. A. Beerel. Journal of Low Power
Electronics 2, 37-44 (2006)
High Performance Asynchronous Design Using Single-Track
Full-Buffer Standard Cells. M. Ferretti and P. A. Beerel. IEEE
Journal of Solid-State Circuits. Vol. 41. No. 6. pp. 1444-1454.
June 2006
The CaSCADE tool
package release was made possible by generous
support from NSF ITR Award No. NSF-CCR-0086036.
The development of the individual tools in
CaSCADE was supported in part by the above
NSF grant, and by some additional funding (see
each downloaded tool individually for further
information).
